In order to meet requirements of increasing the withstand voltage of the semiconductor device and reducing the ON resistance of the semiconductor device, semiconductor devices having the SJ structure are being developed. This type of semiconductor device is generally formed by using a semiconductor layer that is continuously formed over the area extending from the cell region to the peripheral region. In many cases, the SJ structure is formed at the center side region of the semiconductor layer, and a peripheral semiconductor layer making a circuit of the SJ structure is formed at the peripheral side. In the SJ structure, a combination of an n-type column including n-type impurities and a p-type column including p-type impurities is repetitively formed within a plane perpendicular to the layer thickness direction. The peripheral semiconductor layer is formed of a semiconductor including n-type impurities. A p-type body region is formed at the upper area of the SJ structure in the cell region, and a planar type gate electrode or trench type gate electrode is formed so as to confront the p-type body region. A plurality of vertical semiconductor switching cells are formed in the cell region, and execute ON/OFF operation. For example, JP-A-2003-273355 (see FIG. 14) and JP-A-2004-14554 disclose this type of semiconductor device.
An avalanche breakdown resistance testing of a semiconductor device is carried out by an L load surge breakdown resistance testing or the like. In the L load surge breakdown resistance testing, the semiconductor device is forced to induce breakdown therein. The breakdown occurs in an area beyond the critical electric field intensity. Considering the ratio in area between the cell region and the peripheral region, avalanche energy per unit area can be reduced to a smaller value by inducing breakdown at the cell region side having a larger area as compared with a case where breakdown is induced at the peripheral region side having a smaller area. Therefore, by inducing the breakdown at the cell region side, excessive avalanche energy can be suppressed from being locally consumed, and thus there can be avoided such a situation that the semiconductor device is broken. In order to achieve the above phenomenon, the withstand voltage of the peripheral region is set to be larger than the withstand voltage of the cell region so that breakdown occurs preferentially in the cell region.
However, the semiconductor device disclosed in JP-A-2003-273355 cannot achieve the state that the withstand voltage of the peripheral region is higher than the withstand voltage of the cell region. The above publication proposes a structure that the concentration of the impurities of the peripheral semiconductor layer is reduced and plural p-type guard ring regions making a circuit of the cell region are provided at the upper area of the peripheral semiconductor layer. By reducing the concentration of the impurities of the peripheral semiconductor layer, the width of a depletion layer extending in the lateral direction in the peripheral semiconductor layer can be increased. Furthermore, by forming the p-type guard ring regions, the electric field which tends to concentrate in the neighborhood of the boundary between the cell region and the peripheral region can be moderated. By adopting this structure, the electric field which tends to concentrate in the neighborhood of the boundary between the cell region and the peripheral region can be moderated, and a depleted region expanding in the lateral direction can be sufficiently achieved, so that the withstand voltage of the peripheral region is determined by the width in the longitudinal direction of the depleted region.
Since the concentration of the impurities of the p-type guard ring is set to a relatively high value, and thus the depletion layer slightly extends into the p-type guard ring. Accordingly, the width in the longitudinal direction of the depleted region of the peripheral region is substantially equal to a value achieved by subtracting the depth of the p-type guard ring from the layer thickness of the peripheral semiconductor layer. On the other hand, the width in the longitudinal direction of the depleted region of the cell region is equal to the width achieved by subtracting the depth of the p-type body region from the layer thickness of the semiconductor layer, that is, the width in the longitudinal direction of the SJ structure.
The p-type body region and the p-type guard ring are substantially equal in depth to each other, and thus the width in the longitudinal direction of the depleted region of the cell region is substantially equal to the width in the longitudinal direction of the depleted region of the peripheral region. If the depth of the p-type body region is needlessly increased, the withstand voltage of the peripheral region can be set to be higher than the withstand voltage of the cell region, however, the withstand voltage of the cell region is sacrificed. The limitation of the conventional structure resides in that the withstand voltage of the peripheral region is increased to be equal to the withstand voltage of the cell region at maximum, and it cannot be increased to be larger than the withstand voltage of the cell region.